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1 pi6lc48p0301a pi6c20800b block diagram description te pi6lc48p0301a is a 3-output lvpecl synthesizer opti - mized to generate ethernet reference clock frequencies and is a member of pericoms hiflex tm family of high performance clock solutions. using a 25mhz or other fundamental frequency crystal, the most popular ethernet frequencies can be generated based on the settings of 4 frequency select pins. te pi6lc48p0301a uses pericoms proprietary low phase noise pll technology to achieve ultra low phase jitter, so it is ideal for ethernet interface in all kind of systems. features ? ? tree diferential lvpecl output pairs ? ? selectable crystal oscillator interface or lvcmos/lvttl single-ended clock input ? ? supports the following output frequencies: 125mhz, 156.25mhz, 312.5mhz, 625mhz ? ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (12khz C 20mhz): 0.26ps (typical) ? ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (12khz C 20mhz): 0.4ps (max) ? ? full 3.3v or 2.5v supply modes ? ? commercial and industrial ambient operating temperature ? ? available in lead-free package: 28-tqfn applications ? ? networking systems pfd vco m osc xtal_out xtal_in ref_in in_sel# pll_bypass# /a /b fbn m_reset nb_sel[0:1] clka clka# oea clkb0 clkb0# oeb clkb1 clkb1# na_sel[0:1] 3-output lvpecl networking clock generator www.pericom.com pi6lc48p0301a rev . a 06/03/2014 14-0083
2 pinout table pin no. pin name i/o ty pe description 1 m_reset input pull-down master reset. when high, clkx goes to low and clkx# goes to high; when low outputs are enabled. 2 vddoa power bank a output power supply 3, 4 clka, clka# output bank a lvpecl output clock 5 oeb input pull-up bank b output enable. when low, output is diferential low. 6, 9, 14, 19, 22 gnd ground ground 7 oea input pull-up bank a output enable. when low, output is diferential low. 8 fbn input pull-down feedback divider select 10 vdda power analog power supply 11 vdd power core power supply 12, 13 na_sel0, na_sel1 input pull-up bank a output divider select 15, 16 xtal_out, xtal_in crystal crystal input and output 17 ref_in input pull-down cmos reference clock input 18 in_sel# input pull-up when high, crystal is selected; when low, reference input is selected. pin configuration 2 3 fbn 4 gnd 5 m_reset 6 7 in_sel# 8 clkb1 clka clka# gnd 23 22 21 clkb0# ref_in 9 gnd 20 xtal_in 11 vdd 19 clkb1# 18 16 17 na_sel0 gnd 12 oeb gnd 10 vdda xtal_out 15 13 gnd na_sel1 14 28 27 26 25 pll_nypass# nb_sel0 nb_sel1 vddob 1 24 vddoa oea clkb0 www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
3 pin no. pin name i/o ty pe description 20, 21 clkb1#, clkb1 output bank b lvpecl output clock 1 23, 24 clkb0#, clkb0 output bank b lvpecl output clock 0 25 vddob power bank b output power supply 26, 27 nb_sel1, nb_sel0 input pull-up bank b output divider select 28 pll_bypass# input pull-up active low pll bypass bank a frequency table input feedback divider bank a output divider clka/clka# output frequency (mhz) crystal frequency (mhz) fbn na_sel1 na_sel0 25 0 0 0 25 1 625 25 0 0 1 25 2 312.5 20 0 0 1 25 2 250 22.5 0 1 0 25 3 187.5 25 0 1 1 25 4 156.25 24 0 1 1 25 4 150 20 0 1 1 25 4 125 19.44 1 0 0 32 1 622.08 19.44 1 0 1 32 2 311.04 15.625 1 0 1 32 2 250 18.75 1 1 0 32 3 200 19.44 1 1 1 32 4 155.52 18.75 1 1 1 32 4 150 15.625 1 1 1 32 4 125 www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
4 bank b frequency table input feedback divider bank b output divider clkb0/clkb0#, clkb1/clkb1# output frequency (mhz) crystal frequency (mhz) fbn nb_sel1 nb_sel0 25 0 0 0 25 2 312.5 20 0 0 0 25 2 250 25 0 0 1 25 4 156.25 24 0 0 1 25 4 150 20 0 0 1 25 4 125 25 0 1 0 25 5 125 25 0 1 1 25 8 78.125 24 0 1 1 25 8 75 20 0 1 1 25 8 62.5 19.44 1 0 0 32 2 311.04 15.625 1 0 0 32 2 250 19.44 1 0 1 32 4 155.52 18.75 1 0 1 32 4 150 15.625 1 0 1 32 4 125 15.625 1 1 0 32 5 100 19.44 1 1 1 32 8 77.76 18.75 1 1 1 32 8 75 15.625 1 1 1 32 8 62.5 typical crystal requirement parameter minimum ty pica l maximum units mode of oscillation fundamental frequency fbn = 0 19.6 27.2 mhz fbn = 1 15.313 21.25 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf drive level 1 mw recomended crystal specification pericom recommends: a) fl2500047, smd 3.2x2.5(4p), 25mhz, cl=18pf, +/-20ppm http://www.pericom.com/pdf/datasheets/se/fl.pdf b) b) fy2500091, smd 5x3.2(4p), 25mhz, cl=18pf, +/-30ppm http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
5 maximum ratings (over operating free-air temperature range) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. storage temperature .............................................. -65oc to+155oc ambient temperature with power applied ......... -40oc to+85oc 3.3v analog supply voltage ...................................... -0.5 to +3.6v esd protection (hbm) ......................................................... 2000v dc electrical characteristics power supply dc characterisitcs, (t a = -40 to 85oc) symbol parameter condition min ty p max units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo_a v ddo_b output supply voltage 3.135 3.3 3.465 v v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage 2.375 2.5 2.625 v v ddo_a v ddo_b output supply voltage 2.375 2.5 2.625 v i gnd power supply current 150 ma i dda analog supply current 37 ma lvcmos/lvttl dc characterisitcs, (t a = -40 to 85oc) symbol parameter condition min ty p max units v ih input high voltage v dd = 3.3 v +/- 5% 2 v dd + 0.3 v v dd = 2.5 v +/- 5% 1.7 v dd + 0.3 v il input low voltage v dd = 3.3 v +/- 5% -0.3 0.8 v v dd = 2.5 v +/- 5% -0.3 0.7 v i ih input high current ref_in, fbn, m_reset v dd = v in = 3.465v 150 a oea, oeb, pll_by - pass#, in_sel#, na_ sel[1:0], nb_sel[1:0] v dd = v in = 3.465v 5 a i il input low current ref_in, fbn, m_reset v dd = 3.4 65 v, v in = 0v -5 a oea, oeb, pll_by - pass#, in_sel#, na_ sel[1:0], nb_sel[1:0] v dd = 3.4 65 v, v in = 0v -150 a www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
6 lvpecl dc characterisitcs, (t a = -40 to 85oc) symbol parameter condition min ty p max units v oh output high voltage (1) v dd = 3.3v 1.9 2.4 v v dd = 2.5v 1.1 1.6 v ol output low voltage (1) v dd = 3.3v 1.2 1.6 v v dd = 2.5v 0.4 0.8 note: 1. lvpecl termination: source 150ohm to gnd and 100ohm across clk and clk#. www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
7 ac electrical characteristics lvpecl termination: source 150ohm to gnd and using 0.01uf ac-coupled to 50ohm to gnd ac characterisitcs, (t a = -40 to 85oc) symbol parameter condition min. ty p. max units f out output frequency range otuput divider = 1 490 680 mhz otuput divider = 2 245 340 mhz otuput divider = 3 163.33 226.67 mhz otuput divider = 4 122.5 170 mhz otuput divider = 5 98 136 mhz otuput divider = 8 61.25 85 mhz t sk(b) bank skew (1) 25 ps t sk(o) output skew (2,4) output @ same frequencies 70 ps output @ diferent frequencies 200 ps t jit(?) rms phase jitter, (random) (3) 625mhz, (1.875mhz - 20mhz) 0.14 ps 625mhz, (12khz - 20mhz) 0.32 0.4 ps 312.5mhz, (1.875mhz - 20mhz) 0.15 ps 312.5mhz, (12khz - 20mhz) 0.29 0.4 ps 156.25mhz, (1.875mhz - 20mhz) 0.14 ps 156.25mhz, (12khz - 20mhz) 0.26 0.4 ps 125mhz, (1.875mhz - 20mhz) 0.17 ps 125mhz, (12khz - 20mhz) 0.29 0.4 ps t r / t f output rise/fall time 20% to 80% 400 ps o dc output duty cycle measured at the dif - ferential cross point otuput divider = 1 47 53 % other divider values 47 53 % note: 1. defned as skew within a bank of outputs at the same supply voltage and with equal load conditions. 2. defned as skew between outputs at the same supply voltage and with equal load conditions. measured at the diferential cross points. 3. please refer to the phase noise plots. 4. tis parameter is defned in accordance with jedec standard 65. www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
8 phase noise plots f out = 625mhz f out = 312.5mhz f out = 156.25mhz f out = 125mhz www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
9 lvpecl test circuit power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. te pi6lc48p0301a provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda and v ddo should be individually connected to the power supply plane through vias, and 0.1f bypass capacitors should be used for each pin. figure below illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. 50 150 0.01f z = 50 l = 0 ~ 10in 150 device o z = 50 o 50 0.01f v dd 0.1f 0.1f 10f 10? * 3.3v or 2.5v v dda * if v dd is 2.5v, the resistor value will be dierent, see app note for details www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
10 recommendations for unused input and output pins inputs: crystal inputs: for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be lef foating. a 1k resistor can be tied from xtal_in to ground for additional protection. ref_in input: for applications not requiring the use of the clock, it can be lef foating. a 1k resistor tied from the ref_in to ground can provide additional protection. lvcmos control pins: all control pins have internal pulldowns/pullups; a 1k resistor tied from internal pulldown control pins to ground, and a 4.7k tied from internal pullup control pins to power supply can provide additional protection. outputs: lvpecl outputs: all unused lvpecl outputs can be lef foating. crystal input interface te clock generator has been characterized with 18pf parallel resonant crystals. te capacitor values shown in the fgure below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 22pf c2 22pf xtal_in xtal_out x1 18pf parallel crystal www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
11 lvcmos to xtal interface te xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in the fgure below. te xtal_out pin can be lef foating. te input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. tis confguration requires that the output impedance of the driver (ro) plus the series resis - tance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. tis can be done in one of the two ways. first, r1 and r2 in parallel should equal the transmission line empedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50. by overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. v r2 50 dd ro rs zo = ro + rs r1 xtal_in xtal_out v dd 0.1f thermal information symbol description condition q ja junction-to-ambient thermal resistance still air 41.68 o c/w q jc junction-to-case thermal resistance 23.78 o c/w www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083
12 ordering information ordering code packaging type package description operating temperature PI6LC48P0301AZHE zh pb-free & green, 28-pin tqfn commercial pi6lc48p0301azhie zh pb-free & green, 28-pin tqfn industrial notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 28-contact tqfn (zh) www.pericom.com pi6lc48p0301a rev . a 06/03/2014 pi6lc48p0301a 3-output lvpecl networking clock generator 14-0083

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